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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8326 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 high output power programmable catv line driver functional block diagram diff or single input amp attenuation core z out diff = 75 8 8 8 z in (single) = 800 z in (diff) = 1.6k ad8326 daten data clk v ee (10 pins) txen sleep v out+ v outC v cc (7 pins) v in+ v inC vernier decode data latch shift register power-down logic power amp byp gnd features supports docsis standard for reverse path transmission gain programmable in 0.75 db steps over a 53.5 db range low distortion at 65 dbmv output C62 dbc sfdr at 21 mhz C58 dbc sfdr at 65 mhz 1 db compression of 25 dbm at 10 mhz output noise level C45 dbmv in 160 khz maintains 75 output impedance power-up and power-down condition upper bandwidth: 100 mhz (full gain range) single or dual supply operation applications gain-programmable line driver catv telephony modems catv terminal devices general-purpose digitally controlled variable gain block C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 5 15 25 35 45 55 65 distortion C dbc frequency C mhz arp(v s = +12v) are(v s = 5v) arp(v o = 69dbmv) arp(v o = 67dbmv) are(v o = 65dbmv) are(v o = 62dbmv) figure 1. worst harmonic distortion vs. frequency general description the ad8326 is a high-output power, digitally controlled, vari- able gain amplifier optimized for coaxial line driving applications such as data and telephony cable modems that are designed to the mcns-docsis upstream standard. an 8-bit serial word determines the desired output gain over a 53.5 db range result- ing in gain changes of 0.75 db/lsb. the ad8326 is offered in two models, each optimized to support the desired output power and resulting performance. the ad8326 comprises a digitally controlled variable attenuator of 0 db to C54 db, that is preceded by a low noise, fixed-gain buffer and is followed by a low distortion high-power amplifier. the ad8326 accepts a differential or single-ended input signal. the output is designed to drive a 75 ? load, such as coaxial cable, although the ad8326 is capable of driving other loads. when driving 67 dbm into a 75 ? load, the ad8326arp provides a worst harmonic of only C59 dbc at 21 mhz and C57 dbc at 42 mhz. w hen driving 65 dbmv into a 75 ? load, the ad8326are provides a worst harmonic of only C62 dbc at 21 mhz and C60 dbc at 42 mhz. the differential output of the ad8326 is compliant with docsis paragraph 4.2.10.2 for spurious emissions during burst on/off transients. in addition, this device has a sleep mode function that reduces the quiescent current to 4 ma. the ad8326 is packaged in a low-cost 28-lead tssop and a 28-lead p (power) soic. both devices have an operatio nal tem- perature range of C40 c to +85 c.
rev. 0 C2C ad8326?pecifications (t a = 25 c, v s = 12 v, r l = r in = 75 , v in = 259 mv p-p, v out measured through a 1:1 transformer with an insertion loss of 0.5 db @ 10 mhz, unless otherwise noted.) ad8326arp parameter conditions min typ max unit input characteristics specified ac voltage output = 67 dbmv, max gain 259 mv p-p noise figure max gain, f = 10 mhz 16.6 db input resistance differential input 1600 ? single-ended input 800 ? input capacitance 2pf gain control interface gain range 52.5 53.5 54.5 db maximum gain gain code = 71 dec 26.5 27.5 28.5 db minimum gain gain code = 0 dec C27 C26 C25 db gain scaling factor 0.7526 db/lsb gain linearity error f = 10 mhz, code-to-code 0.2 db output characteristics bandwidth (C3 db) all gain codes 100 mhz bandwidth roll-off f = 65 mhz 1.2 db bandwidth peaking f = 65 mhz 0 db output noise spectral density max gain, f = 10 mhz C28 dbmv in 160 khz min gain, f = 10 mhz C45.5 dbmv in 160 khz transmit disable mode, f = 10 mhz C65 dbmv in 160 khz 1 db compression point max gain, f = 10 mhz 26.5 dbm differential output impedance transmit enable and transmit disable mode 75 20% ? overall performance worst harmonic distortion f = 14 mhz, v out = 67 dbmv @ max gain C59 dbc f = 21 mhz, v out = 67 dbmv @ max gain C59 dbc f = 42 mhz, v out = 67 dbmv @ max gain C57 dbc f = 65 mhz, v out = 67 dbmv @ max gain C55 dbc adjacent channel power 16 qam, v out = 67 dbmv C56 dbc adj ch wid = tr ch wid = 160 ksym/sec output settling due to gain change (t gs ) min to max gain 60 ns due to input step change max gain, v in = 0 v to 0.25 v p-p 30 ns signal isolation min gain, txen = 0, 65 mhz, v in = 0.25 v p-p C85 dbc max gain, txen = 0, 42 mhz, v in = 0.25 v p-p C31 dbc max gain, txen = 0, 65 mhz, v in = 0.25 v p-p C28 dbc all gains, sleep, 65 mhz, v in = 0.25 v p-p C85 dbc power control transmit enable response time (t on ) max gain, v in = 0 250 ns transmit disable response time (t off ) max gain, v in = 0 40 ns between burst transients 1 equivalent output = 31 dbmv 5 mv p-p equivalent output = 61 dbmv 60 mv p-p power supply operating range 11.4 12 12.6 v quiescent current transmit enable mode (txen = 1) 147 157 167 ma transmit disable mode (txen = 0) 38 44 50 ma sleep mode 1.5 4.5 7.5 ma operating temperature C40 +85 c range notes 1 between burst transients measured at the output of diplexer. specifications subject to change without notice.
rev. 0 ad8326 C3C (t a = 25 c, v s = 5 v, r l = r in = 75 , v in = 206 v p-p, v out measured through a 1:1 transformer with an insertion loss of 0.5 db @ 10 mhz, unless otherwise noted.) specifications ad8326are parameter conditions min typ max unit input characteristics specified ac voltage output = 65 dbmv, max gain 206 mv p-p noise figure max gain, f = 10 mhz 16.6 db input resistance differential input 1600 ? single-ended input 800 ? input capacitance 2pf gain control interface gain range 52.5 53.5 54.5 db maximum gain gain code = 71 dec 26.5 27.5 28.5 db minimum gain gain code = 0 dec C27 C26 C25 db gain scaling factor 0.7526 db/lsb gain linearity error f = 10 mhz, code-to-code 0.2 db output characteristics bandwidth (C3 db) all gain codes 100 mhz bandwidth roll-off f = 65 mhz 1.1 db bandwidth peaking f = 65 mhz 0 db output noise spectral density max gain, f = 10 mhz C28 dbmv in 160 khz min gain, f = 10 mhz C45.5 dbmv in 160 khz transmit disable mode, f = 10 mhz C65 dbmv in 160 khz 1 db compression point max gain, f = 10 mhz 25.0 dbm differential output impedance transmit enable and transmit disable mode 75 20% ? overall performance worst harmonic distortion f = 14 mhz, v out = 65 dbmv @ max gain C62 dbc f = 21 mhz, v out = 65 dbmv @ max gain C62 dbc f = 42 mhz, v out = 65 dbmv @ max gain C60 dbc f = 65 mhz, v out = 65 dbmv @ max gain C58 dbc adjacent channel power 16 qam, v out = 65 dbmv C58 dbc adj ch wid = tr ch wid = 160 ksym/sec output settling due to gain change (t gs ) min to max gain 60 ns due to input step change max gain, v in = 0 v to 0.19 v p-p 30 ns signal isolation min gain, txen = 0, 65 mhz, v in = 0.19 v p-p C85 dbc max gain, txen = 0, 42 mhz, v in = 0.19 v p-p C31 dbc max gain, txen = 0, 65 mhz, v in = 0.19 v p-p C28 dbc all gains, sleep, 65 mhz, v in = 0.19 v p-p C85 dbc power control transmit enable response time (t on ) max gain, v in = 0 250 ns transmit disable response time (t off ) max gain, v in = 0 40 ns between burst transients 1 equivalent output = 31 dbmv 5 mv p-p equivalent output = 61 dbmv 60 mv p-p power supply operating range 4.75 5.0 5.25 v quiescent current transmit enable mode (txen = 1) 140 150 160 ma transmit disable mode (txen = 0) 36 42 48 ma sleep mode 1 4 7 ma operating temperature C40 +85 c range notes 1 between burst transients measured at the output of diplexer. specifications subject to change without notice.
rev. 0 ad8326 C4C logic inputs (ttl/cmos compatible logic) parameter min typ max unit logic 1 voltage 2.1 5.0 v logic 0 voltage 0 0.8 v logic 1 current (v inh = 5 v) clk, sdata, daten 020na logic 0 current (v inl = 0 v) clk, sdata, daten C600 C100 na logic 1 current (v inh = 5 v) txen 50 190 a logic 0 current (v inl = 0 v) txen C250 C30 a logic 1 current (v inh = 5 v) sleep 50 190 a logic 0 current (v inl = 0 v) sleep C250 C30 a specifications subject to change without notice. timing requirements parameter min typ max unit clock pulsewidth (t wh ) 16.0 ns clock period (t c ) 32.0 ns setup time sdata vs. clock (t ds ) 5.0 ns setup time daten vs. clock (t es ) 15.0 ns hold time sdata vs. clock (t dh ) 5.0 ns hold time daten vs. clock (t eh ) 3.0 ns input rise and fall times, sdata, daten , clock (t r , t f )10ns specifications subject to change without notice. t es valid data word g1 msb. . . .lsb gain transfer (g1) t ds t eh 8 clock cycles gain transfer (g2) t off t gs analog output signal amplitude (p-p) txen clk sdata daten t on t c t wh valid data word g2 figure 2. serial interface timing valid data bit msb msb-1 msb-2 t ds t dh sdata clk figure 3. sdata timing (full temperature range, v cc = 12 v, t r = t f = 4 ns, f clk = 8 mhz unless otherwise noted.) ( daten , clk, sdata, txen, sleep , v cc = 12 v: full temperature r ange)
rev. 0 ad8326 C5C ordering guide model temperature range package description ja package option ad8326arp C40 c to +85 c 28-lead power soic with slug 23 c/w * rp-28 ad8326arp-reel ad8326arp-eval evaluation board ad8326are C40 c to +85 c 28-lead tssop with exposed pad 39 c/w * re-28 ad8326are-reel AD8326ARE-EVAL evaluation board * thermal resistance measured on semi standard 4-layer board. absolute maximum ratings * supply voltage v cc pins 5, 9, 10, 19, 20, 23, 27 . for arp, max v cc = v ee + 13 v; . . . . . . . . . . . . . . . . . . . . . . . for are, max v cc = v ee + 11 v input voltages pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 v pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . C0.8 v to +5.5 v internal power dissipation tssop epad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 w psop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 w operating temperature range . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering 60 seconds . . . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8326 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 ad8326 C6C pin function descriptions pin no. mnemonic description 1 daten data enable low input. this port controls the 8-bit parallel data latch and shift register. a logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta- neously inhibits serial data transfer into the register. a 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. 2 sdata serial data input. this digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the msb (most significant bit) first and ignored. 3 clk clock input. the clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. a logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. this requires the input serial data word to be valid at or before this clock transition. 4, 28 gnd common external ground reference 5, 9, 10, 19, v cc common positive external supply voltage. a 0.1 f capacitor must decouple each pin. 20, 23, 27 6 txen transmit enable pin. logic 1 powers up the part. 7 sleep low power sleep mode. in the sleep mode, the ad8326s supply current is reduced to 4 ma. a logic 0 powers down the part (high z out state) and a logic 1 powers up the part. 8, 12, 17 nc no connection to these pins. 11, 13, 16, 18, v ee common negative external supply voltage. a 0.1 f capacitor must decouple each pin. 22, 24 14 outC negative output signal 15 out+ positive output signal 21 byp internal bypass. this pin must be externally ac-coupled (0.1 f capacitor). 25 v in+ noninverting input. dc-biased to approximately v cc /2. should be ac-coupled with a 0.1 f capacitor. 26 v inC inverting input. dc-biased to approximately v cc /2. should be ac-coupled with a 0.1 f capacitor. pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad8326 daten gnd sdata v cc clk v in C gnd v in+ v cc v ee txen v cc sleep v ee nc byp v cc v cc v cc v cc v ee v ee nc nc v ee v ee out C out+ nc = no connect
rev. 0 ad8326 C7C 1.0 0.5 0 C 0.5 C 1.0 C 1.5 0 9 18 27 36 45 54 63 72 gain control C decimal gain error C db v s = 12v p o = 67dbmv@ max gain 65mhz 42mhz 5mhz 10mhz tpc 2. gain error vs. gain control 40 30 20 10 0 C 10 C 20 C 30 C 40 0.1 1 10 100 1000 gain C db frequency C mhz 71d 00d 46d v s = 12v v o = 67dbmv @ max gain 23d tpc 3. ac response typical performance characteristics v in+ v in C v cc v ee out C ad8326 byp out+ 0.1 f 0.1 f 1:1 toko 617db-a0070 c l 0.1 f 0.1 f 165 75 75 75 + C v o v cc 10 f 0.1 f +1/2 v in C 1/2 v in 0.1 f 0.1 f 10 f v ee tpc 1. test circuit 1 10 100 32.0 30.5 29.0 27.5 26.0 24.5 23.0 21.5 gain C db frequency C mhz c l = 0pf c l = 10pf c l = 20pf c l = 50pf v s = 12v p out = 67dbmv @ max gain tpc 4. ac response for various cap acitor loads C 26 C 30 C 34 C 38 C 42 C 46 C 50 gain control C decimal output noise C dbmv in 160 khz 0 8 16 24 32 40 48 56 64 72 f = 10mhz txen = 1 v s = 12v +01, 4 !21
rev. 0 ad8326 C8C C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 0 9 18 27 36 45 54 63 72 distortion C dbc gain code C decimal v s = 12v f = 42mhz p o = 67dbmv @ max gain hd3 hd2 tpc 6. harmonic distortion vs. gain code for ad8326-arp C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 5 15 25 35 45 55 65 distortion C dbc frequency C mhz v o = 68dbmv @ max gain v o = 69dbmv @ max gain v o = 67dbmv @ max gain v o = 65dbmv @ max gain v s = 12v(arp) tpc 7. second order harmonic distortion vs. frequency for vari ous output powers C 35 C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 5 15 25 35 45 55 65 v s = +12v(arp) v o = 69dbmv @ max gain v o = 67dbmv @ max gain v o = 65dbmv @ max gain v o = 68dbmv @ max gain distortion C dbc frequency C mhz tpc 8. third order harmonic distortion vs. frequency for vari ous output powers 0 C 10 C 20 C 30 C 40 C 50 C 60 C 70 C 80 C 90 C 100 center 21mhz 100khz/ span 1mhz rbw 500hz rf att 30db vbw 5khz swt 20s unit dbm ch pwr +12.27dbm acp up C 56.72db acp low C 56.71db tpc 9. adjacent channel power for ad8326-arp 190 180 170 160 150 140 130 120 110 1 10 100 1000 impedance C frequency C mhz power-down power-up sleep tpc 10. input impedance vs. fre quency (inputs shunted with 165 ? ) 1000 100 10 1 0.1 1 10 100 1000 impedance C frequency C mhz sleep power-down power-up tpc 11. output impedance vs. frequency
rev. 0 ad8326 C9C distortion C dbc C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 0 9 18 27 36 45 54 63 72 dec code v s = 5v f = 42mhz p o = 65dbmv @ max gain hd3 hd2 tpc 12. harmonic distortion vs. gain control for ad8326-are C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 5 15 25 35 45 55 65 v s = 5v(are) v o = 65dbmv @ max gain v o = 66dbmv @ max gain v o = 64dbmv @ max gain v o = 62dbmv @ max gain distortion C dbc frequency C mhz tpc 13. second order harmonic distortion vs. frequency for vari ous output powers C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 5 15 25 35 45 55 65 distortion C dbc frequency C mhz v o = 66dbmv @ max gain v o = 65dbmv @ max gain v o = 64dbmv @ max gain v o = 62dbmv @ max gain v s = 5v(are) tpc 14. third order harmonic distortion vs. frequency for vari ous output powers 0 C 10 C 20 C 30 C 40 C 50 C 60 C 70 C 80 C 90 C 100 center 21mhz 100khz/ span 1mhz rbw 500hz rf att 30db vbw 5khz swt 20s unit dbm ch pwr +10.41dbm acp up C 58.83db acp low C 59.06db tpc 15. adjacent channel power for ad8326-are 0 C 20 C 40 C 60 C 80 C 100 C 120 0 10 100 1000 isolation C dbc frequency C mhz v s = 12v txen = 1 txen = 0 sleep tpc 16. signal isolation vs. frequency 200 180 160 140 120 100 80 60 40 20 C 40 C 30 C 20 C 10 0 10 20 30 40 50 60 70 80 90 temperature C c supply current C ma v s = 12v(arp) transmit enable transmit disable tpc 17. quiescent current vs. temperature
rev. 0 ad8326 C10C applications general applications the ad8326 is primarily intended for use as the upstream power amplifier (pa), also known as a line driver, in docsis (data over cable service interface specification) certified cable modems, cable telephony systems, and catv set-top boxes. the upstream signal is either a qpsk or qam signal generated by a dsp, a dedicated qpsk/qam modulator, or a dac. in all cases the signal must be low-pass filtered before being applied to the pa in order to filter out-of-band noise and higher order harmonics from the amplified signal. due to the varying distances between the cable modem and the headend, the upstream pa must be capable of varying the output power by applying gain or attenuation. the varying output power of the ad8326 ensures that the signal from the cable modem will have the proper level once it arrives at the headend. the upstream signal path also contains a transformer, a diplexer, and cable split- ters. the ad8326 has been designed to overcome losses associated with these passive components in the upstream cable path, particu- larly in modems that support cable telephony. ad8326arp applications the ad8326arp is in a thermally enhanced psop2 package, and designed for single 12 v supply and output power applica- tions up to +69 dbmv. the ad 8326arp will provide maximum performance in 12 v systems. ad8326are applications the ad8326are is in a tssop package with an exposed ther- mal pad. it is designed for dual 5 v or single 10 v supplies. for applications requiring up to 65 dbmv of output power, lower cost, smaller package, and lower power dissipation, the tssop package is most appropriate. operational description the ad8326 consists of four analog functions in the transmit enable or forward mode. the input amplifier (preamp) can be used single-ended or differentially. if the input is used in the differential configuration, it is imperative that the input signals be 180 degrees out of phase and of equal amplitudes. this will ensure proper gain accuracy and harmonic performance. the preamp stage drives a vernier stage that provides the fine tune gain adjustment. the approximate step resolution of 0.75 db is implemented in this stage and provides a total of approximately 5.25 db of accumulated attenuation. after the vernier stage, a dac provides the bulk of the ad8326s attenuation (8 bits or 48 db). the signals in the preamp and vernier gain blocks are differential to improve the psrr and linearity. a differential current is fed from the dac into the output stage, which amplifies these currents to the appropriate levels necessary to drive a 75 ? load. the output stage utilizes negative feedback to implement a differential 75 ? output impedance, which eliminates the need for external matching resistors needed in typical video (or video filter) termination requirements. spi programming the ad8326 is controlled through a serial peripheral interface (spi) of three digital data lines, clk, daten , and sdata. changing the gain requires 8 bits of data to be streamed into the sdata port. the sequence of loading the sdata register begins on the falling edge of the daten pin, which activates the clk line. with the clk line activated, data on the sdata line is clocked into the serial shift register, most significant bit (msb) first, on the rising edge of the clk pulses. since a 7-bit shift register is used in the ad8326, the msb of the 8-bit word is a dont care bit and is shifted out of the register on the eighth clock pulse. the data is latched into the attenuator core on the rising edge of the daten line. this provides control over the changes in the output signal level. the serial interface timing for the ad8326 is shown in figures 2 and 3. the programmable gain range of the ad8326 is C25.75 db to +27.5 db with steps of 0.75 db. this provides a total gain range of 53.25 db. the ad8326 was characterized with a toko transformer (toko #617db-a0070), and the stated gain values include the losses due to the transformer. for gain codes from 0 through 71 the gain transfer function is: a db db code v = [] 27 5 0 75 71 . C (. ( C ) where a v is the gain in db and code is the decimal equivalent of the 8-bit word. gain codes 0 to 71 provide linear changes in gain. figure 4 shows the gain characteristics of the ad8326 for all possible values in an 8-bit word. note that maximum gain is achieved at code 71. from code 72 through 127 the 5.25 db of attenuation from the vernier stage is being applied over every eight codes, resulting in the saw tooth characteristic at the top of the gain range. because the eighth bit is shifted out of the register, the gain characteristics for codes 128 through 255 are identical to codes 0 through 127, as depicted in figure 4. 28 21 14 7 0 C 7 C 14 C 21 C 28 0 32 64 96 128 160 192 224 256 gain C db gain code C decimal figure 4. gain code vs. gain
rev. 0 ad8326 C11C input bias, impedance, and termination the v in + and v in C inputs have a dc bias level of approxi- mately 1.47 v below v cc /2, therefore the input signal should be ac-coupled using 0.1 f capacitors as seen in the typical application circuit (see figure 5). the differential input impedance of the ad8326 is approxi- mately 1600 ? , while the single-ended input is 800 ? . single-ended inverting input when operating the ad8326 in a single-ended input mode v in + and v in C should be terminated as illustrated in figure 6. on the ad8326 evaluation boards, this termination method requires the removal of r12, r13, r14, r16, r17, and r18. install a 0 ? jumper at r15, an 82.5 ? resistor at r10 for a 75 ? system, and a 39.2 ? resistor at r11 to balance the inputs of the ad8326 evaluation board (figure 11). other input impedance configura- tions may be calculated using the equations in figure 6. ad8326 r10 r11 + C z in = r10||800 r11 = z in ||r10 v in C figure 6. single-ended input impedance the inverting and noninverting inputs of the ad8326 must be balanced for all input configurations. differential input from single-ended source the default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. a toko 1:1 transformer is included on the board for this purpose (t3). enabling the evaluation board for single to differential input conversion requires r15 C r17 to be removed, and 0 ? jumpers must be installed on the placeholders for r13, r14, and r18. for a 75 ? input impedance, r12 should be 78.7 ? . refer to figure 11 for evaluation board schematic. in this configuration, the input signal must be applied to v in C . other input imped- ances may be calculated using the equation in figure 7. v in C ad8326 desired impedance = r12||1600 r12 figure 7. differential signal from single-ended source differential signal source the ad8326 evaluation board is also capable of accepting a differential input signal. this requires the installation of a 165 ? resistor in r12, the removal of r13 C r14, r17 C r18, and the installation of 0 ? jumpers for r15 C r16. this configuration results in a differential input impedance of 150 ? . other differ- ential input impedance configurations may be calculated with the equation in figure 8. v in + ad8326 v in C r12 desired impedance = r12||1600 figure 8. differential input daten sdata clk gnd1 v cc txen sleep gnd v cc v cc v ee gnd v ee v out C gnd v cc v in C v in+ v ee v cc v ee byp v cc v cc v ee gnd v ee v out+ ad8326 v ee txen daten sdata clk 10 f 0.1 f 0.1 f 0.1 f toko 617db-a0070 to diplexer z in = 75 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 165 v in C v in+ z in = 150 10 f v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sleep 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f figure 5. typical applications circuit
rev. 0 ad8326 C12C output bias, impedance, and termination the outputs have a dc bias level of approximately v cc /2, there- fore they should be ac-coupled before being applied to the load. the differential output impedance of the ad8326 is internally maintained at 75 ? , regardless of whether the amplifier is in transmit enable mode or transmit disable mode, eliminating the need for external back termination resistors. a 1:1 transformer is used to couple the amplifier s differential output to the coaxial cable while maintaining a proper impedance match. if the out- put signal is being evaluated on standard 50 ? test equipment, a minimum loss 75 ? C 50 ? pad must be used to provide the test circuit with proper impedance match. single supply operation the 12 v supply should be delivered to each of the v cc pins via a low impedance power bus to ensure that each pin is at the same potential. the power bus should be decoupled to ground using a 10 f tantalum capacitor located close to the ad8326arp. in addition to the 10 f capacitor, each v cc pin should be individually decoupled to ground with 0.1 f ceramic chip capacitors located close to the pins. the pin la beled byp (pin 21) should also be decoupled with a 0.1 f capacitor. the pcb should have a low-impedance ground plane covering all unused portions of the board, except in the area of the input and output traces in close proximity to the ad8326 and output transformer. all ground and v ee pins of the ad8326arp must be connected to the ground plane to ensure proper grounding of all internal nodes. pin 28 and the exposed pad should be connected to ground. dual supply operation the +5 v supply power should be delivered to each of the v cc pins via a low impedance power bus to ensure that each pin is at the same potential. the C 5 v supply should also be delivered to each of the v ee pins with a low impedance bus. the power buses should be decoupled to ground with a 10 f tantalum capacitor located close to the ad8326are. in addition to the 10 f capaci- tor, all v cc , v ee and byp pins should be individually decoupled to ground with 0.1 f ceramic chip capacitors located close to the pins. the pcb should have a low-impe dance ground plane covering all unused portions of the board, except in the area of the input and o utput traces in close proximity to the ad8326 and output transformer. all ground pins of the ad8326are must be connected to the ground plane to ensure proper grounding of all internal nodes. pin 28 and the exposed thermal pad should both be tied to ground. signal integrity layout considerations careful attention to printed circuit board layout details will prevent problems due to board parasitics. proper rf design technique is mandatory. the differential input and output traces should be kept as short as possible. it is also critical to make sure that all differential signal paths are symmetrical in length and width. in addition, the input and output traces should be kept far apart in order to minimize coupling (crosstalk) through the board. following these guidelines will improve the overall performance of the ad8326 in all applications. thermal layout considerations as integrated circuits become denser, smaller, and more power- ful, they often produce more heat. therefore when designing pc boards, the layout must be able to draw heat away from the higher power devices. the ad8326are draws up to 1.5 w when run ning at +65 dbmv with 5 v supplies. the ad8326arp draws a maximum of 2 w at +67 dbmv with a +12 v supply. the following guidelines should be used for both the ad8326are and ad8326arp. first and foremost, the exposed thermal pad should be soldered directly to a substantial ground plane that adequately absorbs heat away from the ad8326 package. this is the simplest, and most important step in thermally managing the power dissipated in the ad8326. increasing the area of copper beneath the ad8326 will lower the thermal resistance in the pcb and more effectively allow air to remove the heat from the pcb, and consequently, from the ad8326. secondly, thermal stitching is a method for increasing thermal capacity of the pcb. additionally, thermal stitching can be used to provide a thermally efficient area onto which the ad 8326 may be soldered. thermal stitching is accomplished by using a number of plated through holes (or vias) densely populated in the solder pad area (but not confined to the size of the tssop or psop2 exposed thermal pad). this technique maximizes the copper area w here the package is attached to the pcb increas- ing the thermal mass or capacity by utilizing more than one copper plane. this method of thermal management should be applied in close proximity to the exposed thermal pad. another important guideline is to utilize a multilayer pcb with the ad8326. lowering the pcb thermal resistance using several layers will generally increase thermal mass resulting in cooler junction temperatures. using the techniques described above and dedicating 2.9 square inches of thermally enhanced pcb area, the ad8326 in either package can operate at safe junction temperatures. figures 12-17 show the above practices in use on the AD8326ARE-EVAL board. initial power-up when the supply is first applied to the ad8326, the gain setting of the amplifier is indeterminate. therefore, as power is first applied to the amplifier, the txen pin should be held low (logic 0), preventing forward signal transmission. after power has been applied to the amplifier, the gain can be set to the desired level by following the procedure in the spi programming and gain adjustment section. the txen pin can then be brought from logic 0 to logic 1, enabling forward signal transmission at the desired gain level. asynchronous power-down the asynchronous txen pin is used to place the ad8326 into between burst mode while maintaining a differential output impedance of 75 ? . applying logic 0 to the txen pin acti- vates the on-chip reverse amplifier, providing a 72% reduction in consumed power. for 12 v operation, the supply current is typically reduced from 159 ma to 44 ma. in this mode of operation, between burst noise is minimized and the amplifier can no longer transmit in the upstream direction. in addition to the t xen pin, the ad8326 also incorporates an asynchro- nous sleep pin, which may be used to further reduce the supply current to approxim ately 4 ma. applying logic 0 to the sleep pin places the amplifier into sleep mode. transitioning into or out of sleep mode will result in a transient voltage at the output of the amplifier.
rev. 0 ad8326 C13C distortion, adjacent channel power, and docsis in order to deliver +58 dbmv of high fidelity output power required by docsis, the pa is required to deliver up to +67 dbmv. this added power is required to compensate for losses associated with the transformer, diplexer, directional coupler, and splitters that may be included in the upstream path of the cable telephony. it should be noted that the ad8326 was characterized with the toko 617db-a0070 transformer. tpc 7, tpc 8, tpc 13, and tpc 14 show the ad8326 second and third harmonic distortion performance versus fundamental frequency for various output power levels. these figures are useful for determining the in band harmonic levels from 5 mhz to 65 mhz. harmonics higher in frequency will be sharply attenuated by the low-pass filter function of the diplexer. another measure of signal integrity is adjacent channel power, commonly referred to as acp. docsis section 4.2.10.1.1 states, spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates. tpc 9 shows the mea- sured acp for a +67 dbmv 16 qam signal taken at the output of the ad8326 evaluation board, through a 75 ? to 50 ? matching pad (5.7 db of loss). the transmit channel width and adjacent channel width in tpc 9 correspond to symbol rates of 160 ksym/sec. table i shows the acp results for the ad8326 for all conditions in docsis table 4-7 adjacent channel spurious emissions. table i. adjacent channel power adjacent channel symbol rate transmit 160k/s 320k/s 640k/s 1280k/s 2560k/s symbol acp acp acp acp acp rate (dbc) (dbc) (dbc) (dbc) (dbc) 160k/s C 57 C 59 C 62 C 63 C 64 320k/s C 57 C 58 C 60 C 62 C 64 640k/s C 55 C 58 C 58 C 60 C 62 1280k/s C 55 C 57 C 58 C 58 C 60 2560k/s C 53 C 56 C 57 C 57 C 57 noise and docsis at minimum gain, the ad8326 output noise spectral density is 13.3 nv/ hz measured at 10 mhz. docsis table 4-8, spuri- ous emissions in 5 mhz to 42 mhz, specifies the output noise for various symbol rates. the calculated noise power in dbmv for 160 ksym/second is: comparing the computed noise power of C 45.5 dbmv to the +8 dbmv signal yields C 53.5 dbc, which meets the required level set forth in docsis table 4-8. as the ad8326 gain is increased from this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal to noise ratio that improves with gain. in transmit disable mode, the output noise spectral density is 1.4 nv/ hz , which results in C 65 dbmv w hen computed over 160 ksym/second . the noise power was measured directly at the output of the transformer. in a typical cable telephony application there will be a 6 db pad, or splitter, which will further attenuate the noise by 6 db. evaluation board features and operation the ad8326 evaluation boards (part # AD8326ARE-EVAL and ad8326arp-eval) and control software can be used to control the ad8326 upstream cable driver via the parallel port of a pc. a standard printer cable connected between the paral- lel port and the evaluation board is used to feed all the necessary data to the ad8326 by means of the windows 9x-based control software. this package provides a means of evaluating the am plifier by providing a convenient way to program the gain/attenuation as well as offering easy control of the asynchronous txen and sleep pins. with this evaluation kit, the ad8326 can be evalu- ated in either a single-ended or differential input configuration. the amplifier can also be evaluated with or without the pulse diplexer in the output signal path. a schematic of the evaluation board is provided in figure 11. output transformer and diplexer a 1:1 transformer is needed to couple the differential outputs of the ad8326 to the cable while maintaining a proper impedance match. the specified transformer is available from toko (part # 617db-a0070); however, m/a-com part # etc-1-1t may also be used. the evaluation board is equipped with the toko transformer, but is also designed to accept the m/a-com trans- former. the pulse diplexer included on the evaluation board provides a high-order low-pass filter function, typically used in the upstream path. to remove the diplexer from the signal path, remove the 0 ? chip resistors at r7 and r19, and install a 0 ? chip resistor at r6 so the output signal is directed away from the diplexer and toward the cable port of the evaluation board (figure 11). the ability of the pulse diplexer to achieve docsis com pliance is neither expressed nor implied by analog devices inc. data on the diplexer should be obtained from pulse. when using the diplexer, be sure to properly terminate the cable port (75 ? ) so that the ad8326 draws minimal current. overshoot on pc printer ports the data lines on some pc parallel printer ports have excessive overshoot that may cause communications problems when pre- sented to the clk pin of the ad8326. the evaluation board was designed to accommodate a series resistor and shunt capaci- tor (r2 and c2 in figure 11) to filter the clk signal if required. installing visual basic control software install the cabdrive_26 software by running setup.exe on disk one of the ad8326 evaluation software. follow on-screen directions and insert disk two when prompted. choose instal- lation directory, and then select the icon in the upper left to complete installation. 20 13 3 160 60 45 5 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += log . C . nv hz khz dbmv
rev. 0 ad8326 C14C running ad8326 software to load the control software, go to start, programs, cabdrive_26, or select the ad8326.exe from the installed directory. once loaded, select the proper parallel port to com- municate with the ad8326 (figure 9). figure 9. parallel port selection controlling gain/attenuation of the ad8326 the slide bar controls the gain/attenuation of the ad8326, which is displayed in db and in v/v. the gain scales 0.75 db per lsb with valid codes from 0 to 71. the gain code from the position of the slide bar is displayed in decimal, binary, and hexadecimal (figure 10). transmit enable and sleep mode the transmit enable and transmit disable buttons select the mode of operation of the ad8326 by asserting logic levels on the asynchronous txen pin. the transmit disable button applies logic 0 to the txen pin, disabling forward transmis- sion while maintaining a 75 ? back termination. the transmit enable button applies logic 1 to the txen pin, enabling the ad8326 for forward transmission. checking the enable s leep mode checkbox applies logic 0 to the asynchronous sleep pin, setting the ad8326 for sleep mode. memory functions the memory section of the software provides a way to alter- nate between two gain settings. the x->m1 button stores the current value of the gain slide bar into memory while the rm1 button recalls the stored value, returning the gain slide bar to the stored level. the same applies to the x->m2 and rm2 buttons. figure 10. control software interface
rev. 0 ad8326 C15C v in C 0 v in + 0 c22 0.1 f c23 0.1 f tp13 r15 dni r12 78.7 r16 dni r14 0 r13 0 r10 dni r11 dni t3 t4 toko1 etc1 4 3 6 2 1 4 3 6 2 1 tp14 toko1 etc1 dni r18 0 r17 dni cable_o v cc v ee agnd tb1 daten sdata clk txen sleep 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 c4 0.1 f c6 0.1 f c5 0.1 f p1 1 p1 16 p1 15 p1 14 p1 13 p1 12 p1 11 p1 10 p1 9 p1 8 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 18 p1 17 p1 19 p1 34 p1 33 p1 32 p1 31 p1 30 p1 29 p1 28 p1 27 p1 26 p1 25 p1 24 p1 23 p1 22 p1 21 p1 20 p1 36 p1 35 w1 tp1 tp2 tp3 tp4 tp5 tp6 w2 r1 0 r3 0 r2 0 c3 dni c2 dni c1 dni + tp7 tp8 tp9 v ee r4 open r5 open c19 10 f c18 0.1 f c17 0.1 f c20 0.1 f c21 0.1 f c16 0.1 f c15 0.1 f c14 0.1 f c13 0.1 f c12 0.1 f c11 0.1 f c10 0.1 f c9 0.1 f c20 0.1 f c7 10 f + tp16 tp17 tp18 tp15 v cc t1 t2 toko1 etc1 4 3 4 3 6 2 1 r6 open r19 0 r9 open r7 0 r8 0 tp10 tp12 tp11 agnd hpp lpp cbl com cx6002 1 9 5 3, 10 C 18 z1 ad8326 agnd 6 2 1 agnd dni hpf_o figure 11. evaluation board schematic
rev. 0 ad8326 C16C figure 12. evaluation board layout (component side)
rev. 0 ad8326 C17C figure 13. evaluation board layout (silkscreen top)
rev. 0 ad8326 C18C figure 14. evaluation board layout (circuit side)
rev. 0 ad8326 C19C figure 15. evaluation board layout (silkscreen bottom)
rev. 0 ad8326 C20C figure 16. evaluation board layout (internal ground plane)
rev. 0 ad8326 C21C figure 17. evaluation board layout (internal power planes)
rev. 0 ad8326 C22C ad8326 evaluation board rev. b ?revised - november 22, 2000 qty. description vendor ref description 2 10 f 16 v. b size tantalum chip capacitor ads# 4-7-24 c7, c19 4 0.1 f 50 v. 1206 size ceramic chip capacitor ads# 4-5-18 c20 C 23 14 0.1 f 25 v. 603 size ceramic chip capacitor ads# 4-12-8 c4 C c6, c8 C c18 90 ? 1/8 w. 1206 size chip resistor ads# 3-18- 88 r1 C r3, r7, r8, r13, r14, r18, r19 1 78.7 ? 1% 1/8 w. 1206 size chip resistor ads# 3-18-194 r12 2 yellow test point [inputs] (bisco tp104-01-04) ads# 12-18-32 tp13, tp14 6 white test point [data] (bisco tp104-0 -09) ads# 12-18-42 tp1 C tp6 1 red test point [vcc] (bisco tp104-01-02) ads# 12-18-43 tp15 1 blue test point [vee] (bisco tp104-01-06) ads# 12-18-62 tp7 3 black test point [agnd] (bisco tp104-01-00) ads# 12-18-44 tp16 C tp18 4 end launch sma connector ads# 12-1-31 vin C , vin+, cable, hpf 1 centronics type 36 pin right-angle connector ads# 12-3-50 p1 1 3 terminal power block (green) ads# 12-19-14 tb1 1 1:1 transformer toko # 617db C a0070 toko t3, t1 1 pulse # cx 6002 diplexer pulse z2 1 ad 8326are (tssop epad) upstream cable driver adi# ad8326xre z1 1 ad 8326are rev. b evaluation pc board adi# ad8326xre-eval eval pcb 4#4 C 40 1/4 inch stainless panhead machine screw ads# 30-1-1 4#4 C 40 3/4 inch long aluminum round standoff ads# 30-16-3 2# 2 C 56 3/8 inch stainless panhead machine screw ads# 30-1-17 (p1 hardware) 2 # 2 steel flat washer ads# 30-6-6 (p1 hardware) 2 # 2 steel internal tooth lockwasher ads# 30-5-2 (p1 hardware) 2 # 2 stainless steel hex. machine nut ads# 30-7-6 (p1 hardware) do not install c1 C c3, r4 C r6, r10, r11, r15 C r17, t2, t4, tp8 C tp12, w1 C w2.
rev. 0 ad8326 C23C 28-lead psop (rp-28) 28 15 14 1 heat slug on bottom 0.539 (13.69) 0.529 (13.44) 0.711 (18.06) 0.701 (17.81) 0.410 (10.41) 0.400 (10.16) 0.299 (7.59) 0.292 (7.42) pin 1 0.189 (4.80) 0.179 (4.55) 0.0125 (0.32) 0.0091 (0.23) 8 0 0.040 (1.27) 0.024 (0.61) 0.016 (0.41) 0.010 (0.25) 45 seating plane 0.004 (0.10) 0.000 (0.00) 0.019 (0.48) 0.014 (0.36) 0.098 (2.49) 0.090 (2.29) 0.050 (1.27) bsc standoff 28-lead htssop (re-28) 0.041 (1.05) 0.039 (1.00) 0.031 (0.80) seating plane 0.047 (1.20) max 0.006 (0.15) 0.000 (0.00) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.177 (4.50) 0.173 (4.40) 0.169 (4.30) 28 15 14 1 0.386 (9.80) 0.382 (9.70) 0.378 (9.60) pin 1 0.252 (6.40) bsc exposed pad on bottom 0.138 (3.55) 0.136 (3.50) 0.134 (3.45) 0.119 (3.05) 0.117 (3.00) 0.115 (2.95) 0.0079 (0.20) 0.0035 (0.09) 8 0 0.030 (0.75) 0.024 (0.60) 0.177 (0.45) controlling dimensions are in millimeters ( mm ) outline dimensions dimensions shown in inches and (mm).
C24C c01856C1.5C7/01(0) printed in u.s.a.

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